80546KF Datasheet, PDF (95/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Signal Definitions
Table 6-1. Signal Definitions (Sheet 9 of 9)
Name
V_CCA
V_{CCA_CACHE}
V_{CC_CACHE_SENSE}
V_{SS_CACHE_SENSE}
V_CCIOPLL
V_CCPLL
V_CCSENSE
V_SSSENSE
VID[5:0]
VIDPWRGD
V_SS
V_SSA
V_{SSA_CACHE}
V_TT
VTTEN
Type
I
I
O
I
I
O
O
I
I
I
I
I
O
Description
V_CCA provides isolated power for the analog portion of the internal PLL’s. Use a
discrete RLC filter to provide clean power.
V_{CCA_CACHE} provides isolated power for the L3 cache PLL. Use a discrete RLC
filter to provide clean power.
V_{CC_CACHE_SENSE} and V_{SS_CACHE_SENSE} provide isolated, low impedance
connections to the processor cache voltage (V_CACHE) and ground (V_SS). They
can be used to sense or measure voltage or ground near the silicon with little
noise.
V_CCIOPLL provides isolated power for digital portion of the internal PLL’s.
The on-die PLL filter solution will not be implemented on this platform. The
V_CCPLL input should be left unconnected.
V_CCSENSE and V_SSSENSE provide isolated, low impedance connections to the
processor core voltage (V_CC) and ground (V_SS). These signals must be con-
nected to the voltage regulator feedback signals, which ensure the output volt-
age (i.e. processor voltage) remains within specification.
VID[5:0] (Voltage ID) pins are used to support automatic selection of V_CC.
These are open drain signals that are driven by the processor and must be
pulled to no more than 3.3 V (+5% tolerance) with a resistor. Conversely, the
V_CC VR output must be disabled prior to the voltage supply for these pins
becoming invalid. The VID pins are needed to support processor voltage
specification variations. See Table 2-3 for definitions of these pins. The V_CC VR
must supply the voltage that is requested by these pins, or disable itself.
The processor requires this input to determine that the supply voltage for
BSEL[1:0], VID[5:0], and CVID[3:0] is stable and within specification.
V_SS is the ground plane for the processor.
V_SSA provides an isolated, internal ground for internal PLL’s. Do not connect
directly to ground. This pin is to be connected to V_CCA and V_CCIOPLL through a
discrete filter circuit.
V_{SSA_CACHE} provides an isolated, internal ground for the L3 cache PLL. Do
not connect directly to ground.
V_TT is the front side bus termination voltage.
VTTEN can be used as an output enable for the V_TT regulator. VTTEN is used
as an electrical key to prevent processors with mechanically-equivalent pinouts
from accidentally booting in a 64-bit Intel^® Xeon™ processor MP with up to
8MB L3 cache platform. Since VTTEN is an open circuit on the processor
package, VTTEN must be pulled up on the motherboard.
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64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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