80546KF Datasheet, PDF (113/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Features
8.4.3
PIROM and Scratch EEPROM Supported SMBus
Transactions
The Processor Information ROM (PIROM) responds to two SMBus packet types: Read Byte and
Write Byte. However, since the PIROM is write-protected, it will acknowledge a Write Byte
command but ignore the data. The Scratch EEPROM responds to Read Byte and Write Byte
commands. Table 8-3 diagrams the Read Byte command. Table 8-4 diagrams the Write Byte
command. Following a write cycle to the scratch ROM, software must allow a minimum of 10 ms
before accessing either ROM of the processor.
In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘R’ represents a read bit,
‘W’ represents a write bit, ‘A’ represents an acknowledge (ACK), and ‘///’ represents a negative
acknowledge (NACK). The shaded bits are transmitted by the Processor Information ROM or
Scratch EEPROM, and the bits that aren’t shaded are transmitted by the SMBus host controller. In
the tables, the data addresses indicate 8 bits. The SMBus host controller should transmit 8 bits with
the most significant bit indicating which section of the EEPROM is to be addressed: the Processor
Information ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).
Table 8-3. Read Byte SMBus Packet
S
Slave
Address
1 7-bits
Write
1
A
Command
Code
A
S
Slave
Address
Read
A
1 8-bits 1 1 7-bits
1
1
Data
8-bits
///
P
1
1
Table 8-4. Write Byte SMBus Packet
S
Slave Address
1
7-bits
Write
1
A Command Code A
1
8-bits
1
Data
8-bits
AP
11
8.4.4
SMBus Thermal Sensor
The processor’s SMBus thermal sensor provides a means of acquiring thermal data from the
processor. The thermal sensor is composed of control logic, SMBus interface logic, a precision
analog-to-digital converter, and a precision current source. The sensor drives a small current
through the p-n junction of a thermal diode located on the processor core. The forward bias voltage
generated across the thermal diode is sensed and the precision A/D converter derives a single byte
of thermal reference data, or a “thermal byte reading.” The nominal precision of the least
significant bit of a thermal byte is 1° Celsius.
The processor incorporates the SMBus thermal sensor onto the processor package. Upper and
lower thermal reference thresholds can be individually programmed for the SMBus thermal sensor.
Comparator circuits sample the register where the single byte of thermal data (thermal byte
reading) is stored. These circuits compare the single-byte result against programmable threshold
bytes. If enabled, the alert signal on the processor SMBus (SM_ALERT#) will be asserted when
the sensor detects that either threshold is reached or crossed. Analysis of SMBus thermal sensor
data may be useful in detecting changes in the system environment that may require attention.
The processor SMBus thermal sensor may be used to monitor long term temperature trends, but
can not be used to manage the short term temperature of the processor or predict the activation of
the thermal control circuit. As mentioned earlier, the processor’s high thermal ramp rates make this
infeasible. Refer to the thermal design guidelines listed in Section 1.2 for more details.
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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