80546KF Datasheet, PDF (29/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Electrical Specifications
Table 2-9. Voltage and Current Specifications
Symbol
Parameter
Core
Freq
Min
V_CC
V_CC for processor core
FMB
VID Transition
VID step size during
transition
Total allowable DC load line
shift from VID steps
V_CACHE
V_CC for processor L3 cache
V_TT
FSB termination voltage
(DC specification)
All freq.
All freq.
All freq.
All freq.
V_TT
SM_VCC
I_CC
I_{CC_TDC}
I_CACHE
I_TT
I_TT
I_{SM_VCC}
I_{SGnt_CORE}
I_{SGnt_CACHE}
I_TCC
I_{CC VCCA}
I_{CC VCCIOPLL}
I_CC
VCCA_CACHE
I_{CC GTLREF}
FSB termination voltage
(AC specification)
SMBus supply voltage
I_CC for processor core
Thermal Design Current
(TDC)
I_CC for processor L3 cache
FSB termination current,
post power good
FSB mid-agent current,
post power good
I_CC for SMBus supply
I_CC Stop-Grant Core
I_CC Stop-Grant Cache
I_CC TCC active
I_CC for PLL pin
I_CC for I/O PLL pin
I_CC for L3 cache PLL pin
I_CC per GTLREF pin
All freq.
All freq.
FMB
FMB
All freq
All freq.
All freq.
All freq.
All freq.
All freq.
All freq.
All freq.
All freq.
All freq.
All freq.
1.125
1.176
1.140
3.135
Typ
Refer to
Table 2-10
1.20
1.20
3.300
100
Max
VID Unit Notes
1,2,3,
1.3875 V
4,5,7
± 12.5 mV
18
CVID
1.224
1.260
3.465
91
86
24
4
450
1.275
mV
19
V
17
11,12,
V
13
11,12,
V
13,14
V
13
A
7,10
A
20
A
A 11,15,21
1.3
122.5
56
23
I_CC
60
60
60
200
A 11,16,21
mA
11
A
6,9
A
6,9
A
8
mA
mA
mA
µA
NOTES:
1. These voltages and frequencies are targets only. A variable voltage source should exist on systems in the event that a different
voltage is required. See Section 2.2 and Table 2-3 for more information.
2. The voltage specification requirements are measured across the V_CCSENSE and V_SSSENSE pins using an oscilloscope set to a
100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 MΩ minimum impedance at the processor socket.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not
coupled into the scope probe.
3. Refer to Table 2-10 for the minimum, typical, and maximum V_CC allowed for a given current. The processor should not be
subjected to any V_CC and I_CC combination wherein V_CC exceeds V_{CC_MAX} for a given current.
4. Moreover, V_CC should never exceed the VID voltage. Failure to adhere to this specification can shorten the processor lifetime.
5. V_{CC_MIN} and V_{CC_MAX} are defined at the frequency’s associated I_{CC_MAX} on the V_CC load line.
6. The current specified is also for the HALT State.
7. FMB is the Flexible Motherboard guideline. These guidelines are for estimation purposes only. See Section 2.10.1 for further
details on FMB guidelines.
8. The maximum instantaneous current the processor will draw while the thermal control circuit (TCC) is active as indicated by the
assertion of PROCHOT# is the same as the maximum I_CC for the processor.
9. The core and cache portions of Stop-Grant current is specified at V_CC and V_CACHE max.
10.I_{CC_MAX} is specified at the relative V_{CC_MAX} point on the V_CC load line.
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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