80546KF Datasheet, PDF (105/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

8 Features
8.1
Power-On Configuration Options
Several configuration options can be set by hardware. The processor samples its hardware
configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these
options, refer to Table 8-1.
The sampled information configures the processor for subsequent operation. These configuration
options can only be changed by another reset. All resets configure the processor. For reset
purposes, the processor does not distinguish between a “warm” reset and a “power-on” reset.
Table 8-1. Power-On Configuration Option Pins
Configuration Option
Output tri state
Execute BIST (Built-In Self Test)
In Order Queue de-pipelining (set IOQ depth to 1)
Disable MCERR# observation
Disable BINIT# observation
APIC cluster ID
Disable bus parking
Core Frequency-to-Front Side Bus Multiplier
Symmetric agent arbitration ID
Disable Hyper-Threading Technology
(HT Technology)
Pin^1,2
SMI#
or
A[39]# for Arb ID 3 (middle agent)
A[36]# for Arb ID 0 (end agent)
INIT# or A[3]#
A[7]#
A[9]#
A[10]#
A[12:11]#
A[15]#
A[21:16]#
BR[1:0]#
A[31]#
NOTE:
1. Asserting this signal during RESET# selects the corresponding option.
2. Address pins not identified in this table as configuration options should not be asserted during RESET#.
8.2
Clock Control and Low Power States
The processor allows the use of HALT and Stop-Grant states to reduce power consumption by
stopping the clock to internal sections of the processor, depending on each particular state. See
Figure 8-1 for a visual representation of the processor low power states.
The processor adds support for Enhanced HALT power down state. Refer to Figure 8-1 and the
following sections.
The Stop-Grant state requires chipset and BIOS support on multiprocessor systems. In a
multiprocessor system, all the STPCLK# signals are bussed together, thus all processors are
affected in unison. The Hyper-Threading Technology feature adds the conditions that all logical
processors share the same STPCLK# signal internally. When the STPCLK# signal is asserted, the
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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