80546KF Datasheet, PDF (24/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Electrical Specifications
2.4
2.5
Reserved, Unused, and TESTHI Pins
All RESERVED pins must be left unconnected. Connection of these pins to V_CC, V_SS, or to any
other signal (including each other) can result in component malfunction or incompatibility with
future processors. See Section 5 for a pin listing for the processor and the location of all
RESERVED pins.
For reliable operation, always terminate unused inputs or bidirectional signals to their respective
deasserted states. On-die termination has been included on the processor to allow signals to be
terminated within the processor silicon. Most unused AGTL+ inputs may be left as no-connects
since AGTL+ termination is provided on the processor silicon. See Table 2-6 for details on AGTL+
signals that do not include on-die termination. Unused active-high inputs should be connected
through a resistor to ground (V_SS). Unused outputs may be left unconnected. However, this may
interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing.
A resistor must be used when tying bidirectional signals to power or ground. When tying any signal
to power or ground, a resistor will also allow for system testability. For unused AGTL+ input or I/O
signals, use pull-up resistors of the same value as the on-die termination resistors (R_TT). See
Table 2-15.
Most TAP signals, GTL+ asynchronous inputs, and GTL+ asynchronous outputs do not include on-
die termination (see Table 2-6 for those signals which do not have on-die termination). Inputs and
used outputs must be terminated on the system board. Unused outputs may be terminated on the
system board or left connected. Note that leaving unused outputs unterminated may interfere with
some TAP functions, complicate debug probing, and prevent boundary scan testing.
The TESTHI pins should be tied to V_TT using a matched resistor, where a matched resistor has a
resistance value within ±20% of the impedance of the board transmission line traces. For example,
if the trace impedance is 50 W, then a value between 40 W and 60 W is required.
The TESTHI pins may use individual pull-up resistors or be grouped together as detailed below.
Please note that utilization of boundary scan test will not be functional if pins are connected
together. A matched resistor should be used for each group:
• TESTHI[3:0]
• TESTHI[6:5]
• TESTHI4 — cannot be grouped with other TESTHI signals
Mixing Processors
Intel supports and validates multi-processor configurations in which all processors operate with the
same front side bus frequency and internal cache sizes. Intel does not support or validate operation
of processors with different cache sizes. Mixing different processor steppings but the same model
(as per the CPUID instruction) is supported. Details on CPUID are provided in the Processor BIOS
Writers Guide document and the AP-485 Intel^® Processor Identification and the CPUID
Instruction application note.
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64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet