80546KF Datasheet, PDF (26/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Electrical Specifications
Table 2-5. Front Side Bus Pin Groups (Sheet 2 of 2)
Signal Group
Front Side Bus Clock Input
Clock
Type
SMBus
Synchronous to SM_CLK
Power/Other
Power/Other
NOTES:
1. Refer to Section 6.1 for signal descriptions.
Signals¹
BCLK[1:0]
SM_ALERT#, SM_CLK, SM_DAT,
SM_EP_A[2:0], SM_TS_A[1:0], SM_WP
BOOT_SELECT, BSEL[1:0], COMP0,
CVID[3:0], GTLREF[3:0], ODTEN,
PWRGOOD, RESERVED, SKTOCC#,
SLEW_CTRL, SM_VCC, TEST_BUS,
TESTHI[6:0], V_CACHE, V_CC, V_CCA,
V_{CCA_CACHE}, V_{CC_CACHE_SENSE}, V_CCIOPLL,
V_CCPLL, V_CCSENSE, VID[5:0], VIDPWRGD,
V_SS, V_SSA, V_{SSA_CACHE}, V_{SS_CACHE_SENSE},
V_SSSENSE, V_TT, VTTEN
Table 2-6. Signal Description Table
Signals with R_TT1
A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BOOT_SELECT², BPRI#, D[63:0]#, DBI[3:0]#,
DBSY#, DEFER#, DEP[7:0]#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, ID[7:0]#, IDS#,
LOCK#, MCERR#, OOD#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
BINIT#, BNR#, HIT#, HITM#, MCERR#
Signals with R_L
NOTES:
1. Signals not included in the “Signals with R_TT” list require termination on the baseboard. Please refer to
Table 2-5 for the signal type and Table 2-13 to Table 2-18 for the corresponding DC specifications.
2. The BOOT_SELECT pin is not terminated to R_TT. It has a 500-5000 Ω internal pullup.
The ODTEN signals enables or disables R_TT. Those signals affected by ODTEN still present R_TT
termination to the signal’s pin when the processor is placed in tri-state mode.
Furthermore, the following signals are not affected when the processor is placed in tri-state mode:
BSEL[1:0], CVID[3:0], SKTOCC#, SM_ALERT#, SM_CLK, SM_DAT, SM_EP_A[2:0],
SM_TS_A[1:0], SM_WP, TEST_BUS, TESTHI[6:0], VID[5:0], and VTTEN.
Table 2-7. Signal Reference Voltages
GTLREF
A20M#, A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#,
BINIT#, BNR#, BPM[5:0]#, BPRI#, BR[3:0]#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DEP[7:0]#,
DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,
FORCEPR#, HIT#, HITM#, ID[7:0]#, IDS#, IGNNE#,
INIT#, LINT0/INTR, LINT1/NMI, LOCK#, MCERR#,
ODTEN, OOD#, REQ[4:0]#, RESET#, RS[2:0]#,
RSP#, SMI#, STPCLK#, TRDY#
V_TT / 2
BOOT_SELECT, PWRGOOD¹, TCK¹, TDI¹, TMS¹,
TRST#¹, VIDPWRGD
NOTES:
1. These signals also have hysteresis added to the reference voltage. See Table 2-16 for more information.
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64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet