80546KF Datasheet, PDF (32/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Electrical Specifications
Figure 2-4. V_CC Static and Transient Tolerance
0
VID - 0.000
Icc [A]
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95
VID - 0.020
VID - 0.040
VCC
Maximum
VID - 0.060
VID - 0.080
VID - 0.100
VID - 0.120
VID - 0.140
VID - 0.160
VCC
Typical
VCC
Minimum
VID - 0.180
NOTES:
1. The V_{CC_MIN} and V_{CC_MAX} load lines represent static and transient limits.
2. Refer to Table 2-9 for processor VID information for V_CC.
3. The load lines specify voltage limits at the die measured at the V_CCSENSE and V_SSSENSE pins. Voltage
regulation feedback for voltage regulator circuits must also be taken from processor V_CCSENSE and
V_SSSENSE pins.
2.10.2 V_CC and V_CACHE Overshoot Specification
The processor can tolerate short transient overshoot events where V_CC exceeds the VID voltage or
where V_CACHE exceeds the CVID voltage when transitioning from a high-to-low current load
condition. This overshoot cannot exceed VID + V_{OS_MAX,} or CVID + V_{OS_MAX}. (V_{OS_MAX} is the
maximum allowable overshoot above VID or CVID). These specifications apply to the processor
die voltage as measured across the V_CCSENSE and V_SSSENSE pins for Vcc, and V_{CC_CACHE_SENSE}
and V_{SS_CACHE_SENSE} pins for CVID.
Table 2-11. V_CC and V_CACHE Overshoot Specification
Symbol
Parameter
Min
V_{OS_MAX}
T_{OS_MAX}
Magnitude of V_CC overshoot
above VID or V_CACHE
overshoot above CVID
Time duration of V_CC
overshoot above VID or
V_CACHE overshoot above CVID
Max
0.025
Units
V
Figure
2-5
Notes
5
µs
2-5
32
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet