80546KF Datasheet, PDF (55/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Front Side Bus Signal Quality Specifications
Table 3-2. Ringback Specifications for PWRGOOD and TAP Signal Groups
Signal Group
Maximum Ringback
Transition (with Input Diodes Present)
PWRGOOD and TAP Low → High
PWRGOOD and TAP High → Low
V_t+(max) to V_t-(max)
V_t-(min) to V_t+(min)
Unit
V
V
Figure
3-3
3-4
NOTES:
1. All signal integrity specifications are measured at the processor core (pads).
2. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
3. All values specified by design characterization.
4. Please see Section 3.1.3 for maximum allowable overshoot.
Notes
1,2,3,4
1,2,3,4
Figure 3-3. Low-to-High Receiver Ringback Tolerance for PWRGOOD and TAP Signals
V_TT
Vt+ (max)
Vt+ (min)
0.5 * V_TT
Vt- (max)
Allowable Ringback
Threshold Region to switch
receiver to a logic 1.
Vss
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
55