80546KF Datasheet, PDF (110/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Features
Figure 8-2. Logical Schematic of SMBus Circuitry
SM_VCC
SM_TS_A0
SM_TS_A1
SM_EP_A0
SM_EP_A1
SM_EP_A2
SM_WP
VCC
A0 _Processor CLK
A1 ^Information DATA
ROM
A2
and
WP
Scratch
EEPROM
(1 Kbit each)
VCC
A0
CLK
A1
DATA
Thermal
Sensor
STDBY#
ALERT#
VSS
VSS
SM_CLK
SM_DAT
SM_ALERT#
NOTE: Actual implementation may vary. This figure is provided to offer a general understanding of the
architecture. All SMBus pull-up and pull-down resistors are 10 kΩ and located on the processor.
8.4.1 Processor Information ROM (PIROM)
The lower half (128 bytes) of the SMBus memory component is an electrically programmed read-
only memory with information about the processor. This information is permanently write-
protected. Table 8-2 shows the data fields and formats provided in the Processor Information ROM
(PIROM).
Table 8-2. Processor Information ROM Format (Sheet 1 of 3)
Offset/Section
# of
Bits
Function
Notes
Header:
00h 8 Data Format Revision
Two 4-bit hex digits
01 - 02h 16 EEPROM Size
Size in bytes (MSB first)
03h 8 Processor Data Address
Byte pointer, 00h if not present
04h
8
Processor Core Data
Address
Byte pointer, 00h if not present
05h 8 L3 Cache Data Address
Byte pointer, 00h if not present
06h 8 Package Data Address
Byte pointer, 00h if not present
07h 8 Part Number Data Address Byte pointer, 00h if not present
08h
8
Thermal Reference Data
Address
Byte pointer, 00h if not present
110
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet