80546KF Datasheet, PDF (38/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Electrical Specifications
Table 2-20. Front Side Bus Differential Clock Specifications
T# Parameter
Min
Nom
Max
FSB Clock Frequency
T1: BCLK[1:0] Period
T2: BCLK[1:0] Period Stability
T3: BCLK[1:0] Rise Time
T4: BCLK[1:0] Fall Time
165.78
5.9982
175
175
166.72
6.0320
175
700
700
Unit
MHz
ns
ps
ps
ps
Figure Notes¹
2-8
2
3,4
5
5
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies based on a
166 MHz BCLK[1:0].
2. The period specified here is the average period. A given period may vary from this specification as governed
by the period stability specification (T2). Min period specification is based on -300 PPM deviation from a 6 ns
period. Max period specification is based on the summation of +300 PPM deviation from a 6 ns period and a
+0.5% maximum variance due to spread spectrum clocking.
3. For the clock jitter specification, refer to the applicable clock driver design specification.
4. In this context, period stability is defined as the worst case timing difference between successive crossover
voltages. In other words, the largest absolute difference between adjacent clock periods must be less than
the period stability.
5. Rise and fall times are measured single-ended between 245 mV and 455 mV of the clock swing.
.
Table 2-21. Front Side Bus Common Clock AC Specifications
T# Parameter
Min
Max
Unit
Figure Notes ^{1, 2}
T10: Common Clock Output Valid Delay
T11: Common Clock Input Setup Time
T12: Common Clock Input Hold Time
T13: RESET# Pulse Width
-0.125
1.470
ns
2-10
3
0.810
N/A
ns
2-10
4
0.355
N/A
ns
2-10
4
1.00
10.00
ms
2-18
5,6,7
NOTES:
1. These parameters are based on design characterization and are not tested.
2. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (V_CROSS) of the
BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the
processor core.
3. Valid delay timings for these signals are specified into the test circuit described in Figure 2-6 and with
GTLREF at 0.63 * V_TT ± 2%.
4. Specification is for a minimum swing defined between V_{IL_MAX} to V_{IH_MIN}. This assumes an edge rate of
0.9 V/ns to 1.2 V/ns.
5. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
6. This should be measured after V_TT and BCLK[1:0] become stable.
7. Maximum specification applies only while PWRGOOD is asserted.
.
Table 2-22. Front Side Bus Source Synchronous AC Specifications (Sheet 1 of 2)
T# Parameter
Min
Typ
Max
Unit
Figure
Notes
1,2,3
T20: Source Sync. Output Valid Delay
(first data/address only)
T21: T_VBD Source Sync. Data Output
Valid Before Data Strobe
T22: T_VAD Source Sync. Data Output
Valid After Data Strobe
-0.150
0.400
0.400
1.400
ns 2-11,2-12
4
ns
2-12
4,7
ns
2-12
4,8
38
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet