80546KF Datasheet, PDF (108/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Features
8.2.4
8.2.4.1
8.2.4.2
8.3
While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] are latched by the processor,
and only serviced when the processor returns to the Normal state. Only one occurrence of each
event is recognized upon return to the Normal state.
While in Stop-Grant state, the processor processes snoops on the front side bus and latches
interrupts delivered on the front side bus.
The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# is asserted if there
is any pending interrupt latched within the processor. Pending interrupts that are blocked by the
EFLAGS.IF bit being clear still cause assertion of PBE#. Assertion of PBE# indicates to system
logic that it should return the processor to the Normal state.
Enhanced HALT Snoop State or HALT Snoop State,
Stop Grant Snoop State
The Enhanced HALT Snoop state is used in conjunction with the Enhanced HALT state. If
Enhanced HALT state is not enabled in the BIOS, the default Snoop state entered will be the HALT
Snoop state. Refer to the sections below for details on HALT Snoop state, Grant Snoop state and
Enhanced HALT Snoop state.
HALT Snoop State, Stop Grant Snoop State
The processor responds to snoop or interrupt transactions on the front side bus while in Stop-Grant
state or in HALT Power Down state. During a snoop or interrupt transaction, the processor enters
the HALT/Grant Snoop state. The processor stays in this state until the snoop on the front side bus
has been serviced (whether by the processor or another agent on the front side bus) or the interrupt
has been latched. After the snoop is serviced or the interrupt is latched, the processor will return to
the Stop-Grant state or HALT Power Down state, as appropriate.
Enhanced HALT Snoop State
The Enhanced HALT Snoop state is the default Snoop state when the Enhanced HALT state is
enabled via the BIOS. The processor remains in the lower bus ratio and VID operating point of the
Enhanced HALT state.
While in the Enhanced HALT Snoop state, snoops and interrupt transactions are handled the same
way as in the HALT Snoop state. After the snoop is serviced or the interrupt is latched, the
processor returns to the Enhanced HALT state.
Enhanced Intel SpeedStep^® Technology
Enhanced Intel SpeedStep technology enables the processor to switch between multiple frequency
and voltage points, which may result in platform power savings. In order to support this
technology, the system must support dynamic VID transitions. Switching between voltage/
frequency states is software controlled.
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64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet