80546KF Datasheet, PDF (5/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

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Debug Tools Specifications............................................................................................137
10.1 Logic Analyzer Interface (LAI) ...........................................................................137
10.1.1 Mechanical Considerations ..................................................................137
10.1.2 Electrical Considerations......................................................................137
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On-Die Front Side Bus Termination .................................................................... 17
Phase Lock Loop (PLL) Filter Requirements ...................................................... 20
Processor Load Current vs. Time........................................................................ 30
VCC Static and Transient Tolerance................................................................... 32
VCC and VCACHE Overshoot Example Waveform............................................ 33
Electrical Test Circuit........................................................................................... 42
TCK Clock Waveform.......................................................................................... 43
Differential Clock Waveform................................................................................ 43
Differential Clock Crosspoint Specification.......................................................... 44
Front Side Bus Common Clock Valid Delay Timing Waveform........................... 44
Source Synchronous 2X (Address) Timing Waveform........................................ 45
Source Synchronous 4X (Data) Timing Waveform ............................................. 46
TAP Valid Delay Timing Waveform ..................................................................... 47
Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform ... 47
THERMTRIP# Power Down Sequence............................................................... 47
SMBus Timing Waveform.................................................................................... 48
SMBus Valid Delay Timing Waveform ................................................................ 48
Voltage Sequence Timing Requirements............................................................ 49
VIDPWRGD Timing Requirements ..................................................................... 50
FERR#/PBE# Valid Delay Timing ....................................................................... 50
VID Step Timings ................................................................................................ 51
VID Step Times and VCC Waveforms ................................................................ 51
Low-to-High Front Side Bus Receiver Ringback Tolerance ................................ 54
High-to-Low Front Side Bus Receiver Ringback Tolerance ................................ 54
Low-to-High Receiver Ringback Tolerance for PWRGOOD and TAP Signals ... 55
High-to-Low Receiver Ringback Tolerance for PWRGOOD and TAP Signals ... 56
Maximum Acceptable Overshoot/Undershoot Waveform ................................... 60
Processor Package Assembly Sketch.................................................................61
Processor Package Drawing (Sheet 1 of 2) ........................................................ 63
Processor Package Drawing (Sheet 2 of 2) ........................................................ 64
Processor Topside Markings............................................................................... 67
Processor Bottom-Side Markings........................................................................ 67
Processor Pin-Out Coordinates, Top View.......................................................... 68
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Thermal Profile .. 99
Case Temperature (TCASE) Measurement Location .......................................100
Thermal Monitor 2 Frequency and Voltage Ordering ........................................102
Stop Clock State Machine .................................................................................107
Logical Schematic of SMBus Circuitry ..............................................................110
Passive Processor Thermal Solution (3U and larger) .......................................128
Top Side Board Keep-Out Zones (Part 1) .........................................................129
Top Side Board Keep-Out Zones (Part 2) .........................................................130
Bottom Side Board Keep-Out Zones.................................................................131
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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