80546KF Datasheet, PDF (120/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Features
Table 8-16. Memory Device SMBus Addressing (Sheet 2 of 2)
Address Upper
(Hex)
Address¹
Device Select
R/W
A6h/A7h
A8h/A9h
AAh/ABh
ACh/ADh
AEh/AFh
bits 7-4
1010
1010
1010
1010
1010
SM_EP_A2
bit 3
0
1
1
1
1
SM_EP_A1
bit 2
1
0
0
1
1
SM_EP_A0
bit 1
1
0
1
0
1
bit 0
X
X
X
X
X
NOTE:
1. This addressing scheme will support up to 8 processors on a single SMBus.
8.4.9 Managing Data in the PIROM
The PIROM consists of the following sections:
• Header
• Processor Data
• Processor Core Data
• Cache Data
• Package Data
• Part Number Data
• Thermal Reference Data
• Feature Data
• Other Data
Details on each of these sections are described below.
Note: Reserved fields or bits SHOULD be programmed to zeros. However, OEMs should not rely on this
model.
8.4.9.1
Header
To maintain backward compatibility, the Header defines the starting address for each subsequent
section of the PIROM. Software should check for the offset before reading data from a particular
section of the ROM.
Example: Code looking for the cache data of a processor would read offset 05h to find a value of
25h. 25h is the first address within the 'Cache Data' section of the PIROM.
The Header also includes the data format revision at offset 0h and the EEPROM size (formatted in
hex bytes) at offset 01-02h. The data format revision is used whenever fields within the PIROM are
redefined. Normally the revision would begin at a value of 1. If a field, or bit assignment within a
field, is changed such that software needs to discern between the old and new definition, then the
data format revision field should be incremented.
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64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet