80546KF Datasheet, PDF (49/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Electrical Specifications
Figure 2-18. Voltage Sequence Timing Requirements
R eset C onfiguration
S ignals
Tc
BC LK[1:0]
Td
V
TT
V ID [5:0]
Ta
Tb
C V ID [3:0]
B S E L[1:0]
VID PW RG D
V CACH E
VCC
PWRGOOD
RESET#
Te
Ti
Tf
Tg
Th
Ta = T 45 / T47: R eset configuration signals setup tim e
Tb = T 46: R eset configuration signals hold tim e
Tc = T37: B C LK Valid B efore P W R G O O D A ctive
Td = T 71: V TT to V ID P W R G D delay tim e
Te = T73: V ID P W R G D to VCACHE delay tim e
Tf = T41: V CC to PW R G O O D assertion tim e
Tg = T36: P W R G O O D to R ES E T# de-assertion tim e
Th = T 13: R E S ET# pulse w idth
Ti = T74: VCACHE to VCC delay tim e
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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