80546KF Datasheet, PDF (121/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Features
The EEPROM size provides the size of the PIROM in hex bytes. The PIROM is 128 bytes; thus,
offset 01 - 02h would be programmed to 80h.
8.4.9.2
Processor Data
This section contains two pieces of data:
• The S-spec/QDF of the part in ASCII format
• (1) 2-bit field to declare if the part is a pre-production sample or a production unit
The S-spec/QDF field is six ASCII characters wide and is programmed with the same S-spec/QDF
value as marked on the processor. If the value is less than six characters in length, leading spaces
(20h) are programmed in this field.
Example: A processor with a QDF mark of QEU5 contains the following in field 0E-13h: 20, 20,
51, 45, 55, 35h. This data consists of two blanks at 0Eh and 0Fh followed by the ASCII codes for
QEU5 in locations 10 - 13h.
Offset 14h contains the sample/production field, which is a two-bit field and is LSB aligned. All Q-
spec material will use a value of 00b. All S-spec material will use a value of 01b. All other values
are reserved.
Example: A processor with a Qxxx mark (engineering sample) will have offset 14h set to 00b. A
processor with an Sxxxx mark (production unit) will use 01b at offset 14h.
8.4.9.3
Processor Core Data
This section contains core silicon-related data.
8.4.9.3.1 CPUID
The CPUID field is a copy of the results in EAX[13:0] from Function 1 of the CPUID instruction.
Note: The field is not aligned on a byte boundary since the first two bits of the offset are reserved. Thus,
the data must be shifted right by two in order to obtain the same results.
Example: The CPUID of a C-0 stepping 64-bit Intel^® Xeon™ processor MP with up to 8MB L3
cache is 0F41h. The value programmed into offset 16 - 17h of the PIROM is 3D04h.
Note: The first two bits of the PIROM are reserved, as highlighted in the example below.
CPUID instruction results
0000 1111 0100 0001 (0F41h)
PIROM content
0011 1101 0000 0100 (3D04h)
8.4.9.3.2 Front Side Bus Frequency
Offset 1A - 1Bh provides front side bus frequency information. Systems may need to read this
offset to decide if all installed processors support the same front side bus speed. Because the Intel
NetBurst microarchitecture bus is described as a 4X data bus, the frequency given in this field is
currently 667 MHz. The data provided is the speed, rounded to a whole number, and reflected in
hex.
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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