80546KF Datasheet, PDF (118/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Features
8.4.6.5 Conversion Rate Registers
The contents of the Conversion Rate Registers determine the nominal rate at which analog-to-
digital conversions happen when the SMBus thermal sensor is in auto-convert mode. There are two
Conversion Rate Registers: RCR for reading the conversion rate value; and WCR for writing the
value. Table 8-14 shows the mapping between Conversion Rate Register values and the conversion
rate. As indicated in Table 8-10, the Conversion Rate Register is set to its default state of 02h
(0.25 Hz nominally) when the thermal sensor is powered up. There is a ±30% error tolerance
between the conversion rate indicated in the conversion rate register and the actual conversion rate.
Table 8-14. SMBus Thermal Sensor Conversion Rate Registers
Register Value
00h
01h
02h
03h
04h
05h
06h
07h
08h to FFh
Conversion Rate (Hz)
0.0625
0.125
0.25
0.5
1.0
2.0
4.0
8.0
Reserved for future use
8.4.7
8.4.8
SMBus Thermal Sensor Alert Interrupt
The SMBus thermal sensor located on the processor includes the ability to interrupt the SMBus
when a fault condition exists. The fault conditions consist of:
1. a processor thermal diode value measurement that exceeds a user-defined high or low
threshold programmed into the Command Register; or
2. disconnection of the processor thermal diode from the thermal sensor.
The interrupt can be enabled and disabled via the thermal sensor Configuration Register and is
delivered to the system board via the SM_ALERT# open drain output. Once latched, the
SM_ALERT# should only be cleared by reading the Alert Response byte from the Alert Response
Address of the thermal sensor. The Alert Response Address is a special slave address shown in
Table 8-9. The SM_ALERT# will be cleared once the SMBus master device reads the slave ARA
unless the fault condition persists. Reading the Status Register or setting the mask bit within the
Configuration Register does not clear the interrupt.
SMBus Device Addressing
Of the addresses broadcast across the SMBus, the memory component claims those of the form
“1010XXXZb”. The “XXX” bits are defined by pull-up and pull-down resistors on the system
baseboard. These address pins are pulled down weakly (10 kW) on the processor substrate to
ensure that the memory components are in a known state in systems which do not support the
SMBus (or only support a partial implementation). The “Z” bit is the read/write bit for the serial
bus transaction.
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64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet