80546KF Datasheet, PDF (91/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Signal Definitions
Table 6-1. Signal Definitions (Sheet 5 of 9)
Name
ID[7:0]#
IDS#
IERR#
IGNNE#
INIT#
LINT0/INTR
LINT1/NMI
LOCK#
Type
Description
I
ID[7:0]# are the Transaction ID signals. They are driven during the Deferred
Phase by the deferring agent.
I IDS# is the ID Strobe signal. It is asserted to begin the Deferred Phase.
IERR# (Internal Error) is asserted by a processor as the result of an internal
error. Assertion of IERR# is usually accompanied by a SHUTDOWN
O transaction on the processor front side bus. This transaction may optionally be
converted to an external error signal (e.g., NMI) by system core logic. The
processor will keep IERR# asserted until the assertion of RESET#.
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If
IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
I
IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this
signal following an I/O write instruction, it must be valid a 6 clks before the I/O
write’s response.
INIT# (Initialization), when asserted, resets integer registers inside all
processors without affecting their internal caches or floating-point registers.
Each processor then begins execution at the power-on Reset vector configured
during power-on configuration. The processor continues to handle snoop
I
requests during INIT# assertion. INIT# is an asynchronous signal and must
connect the appropriate pins of all processor front side bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then
the processor executes its Built-in Self-Test (BIST).
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all front
side bus agents. When the APIC functionality is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI,
a nonmaskable interrupt. INTR and NMI are backward compatible with the
signals of those names on the Pentium^® processor. Both signals are
I
asynchronous.
These signals must be software configured via BIOS programming of the APIC
register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the
default configuration.
LOCK# indicates to the system that a set of transactions must occur atomically.
This signal must connect the appropriate pins of all processor front side bus
agents. For a locked sequence of transactions, LOCK# is asserted from the
beginning of the first transaction to the end of the last transaction.
I/O
When the priority agent asserts BPRI# to arbitrate for ownership of the
processor front side bus, it will wait until it observes LOCK# deasserted. This
enables symmetric agents to retain ownership of the processor front side bus
throughout the bus locked operation and ensure the atomicity of lock.
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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