80546KF Datasheet, PDF (119/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Features
The thermal sensor internally decodes one of three upper address patterns from the bus of the form
“0011XXXZb”, “1001XXXZb”, or “0101XXXZb”. The device’s addressing, as implemented, uses
the SM_TS_A[1:0] pins in either the HI, LO, or Hi-Z state. Therefore, the thermal sensor supports
nine unique addresses. To set either pin for the Hi-Z state, the pin must be left floating. As before,
the “Z” bit is the read/write bit for the serial transaction.
Note that addresses of the form “0000XXXXb” are Reserved and should not be generated by an
SMBus master. The thermal sensor samples and latches the SM_TS_A[1:0] signals at power-up
and at the starting point of every conversion. System designers should ensure that these signals are
at valid V_IH, V_IL, or floating input levels prior to or while the thermal sensor’s SM_VCC supply
powers up. This should be done by pulling the pins to SM_VCC or V_SS via a 1 kW or smaller
resistor, or leaving the pins floating to achieve the Hi-Z state. If the system designer wants to drive
the SM_TS_A[1:0] pins with logic, the designer must still ensure that the pins are at valid input
levels prior to or while the SM_VCC supply ramps up. The system designer must also ensure that
their particular implementation does not add excessive capacitance to the address inputs. Excess
capacitance at the address inputs may cause address recognition problems.
Figure 8-2 shows a logical diagram of the pin connections. Table 8-15 and Table 8-16 describe the
address pin connections and how they affect the addressing of the devices.
Table 8-15. Thermal Sensor SMBus Addressing
Address (Hex)
Upper
Address¹
Device Select
SM_TS_A1
SM_TS_A0
0
0
3Xh
0011
Z²
0
1
0
0
Z²
5Xh
0101
Z²
Z²
1
Z²
0
1
9Xh
1001
Z²
1
1
1
8-bit Address Word on Serial Bus
b[7:0]
0011000Xb
0011001Xb
0011010Xb
0101001Xb
0101010Xb
0101011Xb
1001100Xb
1001101Xb
1001110Xb
NOTES:
1. Upper address bits are decoded in conjunction with the device select pins.
2. A tri-state or “Z” state on this pin is achieved by leaving this pin unconnected.
Note: System management software must be aware of the processor dependent addresses for the thermal
sensor.
Table 8-16. Memory Device SMBus Addressing (Sheet 1 of 2)
Address Upper
(Hex)
Address¹
Device Select
R/W
A0h/A1h
A2h/A3h
A4h/A5h
bits 7-4
1010
1010
1010
SM_EP_A2
bit 3
0
0
0
SM_EP_A1
bit 2
0
0
1
SM_EP_A0
bit 1
0
1
0
bit 0
X
X
X
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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