80546KF Datasheet, PDF (53/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

3 Front Side Bus Signal Quality
Specifications
3.1
3.1.1
Source synchronous data transfer requires the clean reception of data signals and their associated
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage
swings will adversely affect system timings. Ringback and signal non-monotonicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines. Excessive
signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can
cause device failure if absolute voltage limits are exceeded. Overshoot and undershoot can also
cause timing degradation due to the build up of inter-symbol interference (ISI) effects. For these
reasons, it is crucial that the designer work towards a solution that provides acceptable signal
quality across all systematic variations encountered in volume manufacturing.
This section documents signal quality metrics used to derive topology and routing guidelines
through simulation. All specifications are specified at the processor core (pad measurements).
Specifications for signal quality are for measurements at the processor core only and are only
observable through simulation. The same is true for all front side bus AC timing specifications in
Section 2.12. Therefore, proper simulation of the processor front side bus is the only way to
verify proper timing and signal quality.
Front Side Bus Signal Quality Specifications and
Measurement Guidelines
Ringback Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines.
Table 3-1 provides the signal quality specifications for the AGTL+ and GTL+ asynchronous signal
groups. Table 3-2 demonstrates the signal quality specification for the TAP signal group. These
specifications are for use in simulating signal quality at the processor pads.
Maximum allowable overshoot and undershoot specifications for a given duration of time are
detailed in Table 3-3 through Section 3-6. front side bus ringback tolerance for AGTL+ and GTL+
asynchronous signal groups are shown in Figure 3-1 (low-to-high transitions) and Figure 3-2
(high-to-low transitions).
The TAP signal group includes hysteresis on the input buffers and thus has relaxed ringback
requirements when compared to the other buffer types. Figure 3-3 shows the front side bus
ringback tolerance for low-to-high transitions and Figure 3-4 for high-to-low transitions. The
hysteresis values Vt+ and Vt- can be found in Table 2-16.
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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