80546KF Datasheet, PDF (21/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Electrical Specifications
Individual processor VID values may be calibrated during manufacturing such that two devices at
the same core speed may have different default VID settings. Furthermore, any processor, even
those on the same processor front side bus, can drive different VID settings during normal
operation.
The processor uses six voltage identification pins, VID[5:0], to support automatic selection of
power supply voltages. Table 2-3 specifies the voltage level corresponding to the state of VID[5:0].
A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the
processor socket is empty (i.e. VID[5:0] = x11111), or the voltage regulation circuit cannot supply
the voltage that is requested, the processor’s voltage regulator must disable itself.
The processor provides the ability to operate while transitioning to an adjacent VID and its
associated processor core voltage (V_CC). This will represent a DC shift in the load line. It should be
noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions
as necessary to reach the target core voltage. Transitions above the specified VID are not
permitted. Table 2-9 includes VID step sizes and DC shift ranges. Minimum and maximum
voltages must be maintained as shown in Table 2-10 and Figure 2-4.
The VRM or VRD utilized must be capable of regulating its output to the value defined by the new
VID. DC specifications for VID transitions are included in Table 2-9 and Table 2-10.
Power source characteristics must be guaranteed to be stable whenever the supply to the voltage
regulator is stable.
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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