80546KF Datasheet, PDF (39/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Electrical Specifications
Table 2-22. Front Side Bus Source Synchronous AC Specifications (Sheet 2 of 2)
T# Parameter
Min
Typ
Max
Unit
Figure
Notes
1,2,3
T23: T_VBA Source Sync. Address
Output Valid Before Address Strobe
1.120
T24: T_VAA Source Sync. Address
Output Valid After Address Strobe
1.120
T25: T_SUSS Source Sync. Input Setup
Time to Strobe
0.100
T26: T_HSS Source Sync. Input Hold
Time to Strobe
0.100
T27: T_SUCC Source Sync. Input Setup
Time to BCLK[1:0]
0.910
T29: T_FASS First Address Strobe to
Second Address Strobe
1/2
T30: T_FDSS: First Data Strobe to
Subsequent Strobes
n/4
T31: Data Strobe ‘n’ (DSTBN#) Output
Valid Delay
5.100
T32: Address Strobe Output Valid
Delay
1.350
6.650
2.900
ns
2-11
4,7
ns
2-11
4,8
ns 2-11,2-12
5
ns 2-11,2-12
5
ns 2-11,2-12
6
BCLKs 2-11
9
BCLKs 2-12
10,11
ns
2-12
12
ns
2-11
NOTES:
1. Not 100% tested. These parameters are based on design characterization.
2. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source
synchronous data signals are referenced to the falling edge of their associated data strobe. Source
synchronous address signals are referenced to the rising and falling edge of their associated address strobe.
All source synchronous AGTL+ signal timings are referenced at GTLREF at the processor core.
3. Unless otherwise noted, these specifications apply to both data and address timings.
4. Valid delay timings for these signals are specified into the test circuit described in Figure 2-6 and with
GTLREF at 0.63 * V_TT ± 2%.
5. Specification is for a minimum swing defined between V_{IL_MAX} to V_{IH_MIN}. AC timings are specified as GTLREF
± (0.06 * V_TT). This assumes an edge rate of 0.9 V/ns to 1.2 V/ns.
6. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each
respective strobe.
7. This specification represents the minimum time the data or address will be valid before its strobe.
8. This specification represents the minimum time the data or address will be valid after its strobe.
9. The rising edge of ADSTB# must come approximately 1/2 BCLK period after the falling edge of ADSTB#.
10.For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.
11.The second data strobe (falling edge of DSTBn#) must come approximately 1/4 BCLK period after the first
falling edge of DSTBp#. The third data strobe (falling edge of DSTBp#) must come approximately 1/2 BCLK
period after the first falling edge of DSTBp#. The last data strobe (falling edge of DSTBn#) must come
approximately 3/4 BCLK period after the first falling edge of DSTBp#.
12.This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.
Table 2-23. Miscellaneous Signals AC Specifications (Sheet 1 of 2)
T# Parameter
Min
Max
Unit Figure
T35: GTL+ asynchronous and AGTL+
asynchronous input pulse width
6
BCLKs
T36: PWRGOOD to RESET# deassertion time
1
10
ms
2-18
T37: BCLK valid before PWRGOOD active
10
BCLKs 2-18
Notes
1,2,5
7
3
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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