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Signal Definitions
Table 6-1. Signal Definitions (Sheet 4 of 9)
Name
Type
Description
DBSY#
DEFER#
DEP[7:0]#
DP[3:0]#
DRDY#
DSTBN[3:0]#
DSTBP[3:0]#
FERR#/PBE#
FORCEPR#
GTLREF[3:0]
HIT#
HITM#
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data
I/O
on the processor front side bus to indicate that the data bus is in use. The data
bus is released after DBSY# is deasserted. This signal must connect the
appropriate pins on all processor front side bus agents.
DEFER# is asserted by an agent to indicate that a transaction cannot be
I
guaranteed in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or I/O agent. This signal must connect
the appropriate pins of all processor front side bus agents.
The DEP[7:0]# (data bus ECC protection) signals provide optional ECC
protection for the data bus. They are driven by the agent responsible for driving
D[63:0]#, and, if ECC is implemented, must connect the appropriate pins of all
bus agents which use them.
I/O
Furthermore, the DBI# pins determine the polarity of the ECC signals. Each
pair of 2 ECC signals corresponds to one DBI# signal. When the DBI# signal is
active, the corresponding ECC pair is inverted and therefore sampled active
high.
DP[3:0]# (Data Parity) provide optional parity protection for the data bus. They
I/O
are driven by the agent responsible for driving D[63:0]#, and, if parity is
implemented, must connect the appropriate pins of all bus agents which use
them.
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
I/O
indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of all processor front side bus agents.
I/O Data strobe used to latch in D[63:0]#, DEP[7:0]# and DBI[3:0]#.
I/O Data strobe used to latch in D[63:0]#, DEP[7:0]# and DBI[3:0]#.
FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal
and its meaning is qualified by STPCLK#. When STPCLK# is not asserted,
FERR#/PBE# indicates a floating-point error and will be asserted when the
processor detects an unmasked floating-point error. When STPCLK# is not
asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387
coprocessor, and is included for compatibility with systems using MS-DOS*-
O
type floating-point error reporting. When STPCLK# is asserted, an assertion of
FERR#/PBE# indicates that the processor has a pending break event waiting
for service. The assertion of FERR#/PBE# indicates that the processor should
be returned to the Normal state. For additional information on the pending
break event functionality, including the identification of support of the feature
and enable/disable information, refer to Volume 3 of the IA-32 Intel®
Architecture Software Developer’s Manual and the AP-485 Intel® Processor
Identification and the CPUID Instruction application note.
I This input can be used to force activation of the Thermal Control Circuit.
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
I is used by the AGTL+ receivers to determine if a signal is an electrical 0 or an
electrical 1. Please refer to Table 2-19 for further details.
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Any front side bus agent may assert both HIT# and HITM# together to
indicate that it requires a snoop stall, which can be continued by reasserting
I/O ^{HIT# and HITM# together, every other common clock.}
I/O
Since multiple agents may deliver snoop results at the same time, HIT# and
HITM# are wire-OR signals which must connect the appropriate pins of all
processor front side bus agents. In order to avoid wire-OR glitches associated
with simultaneous edge transitions driven by multiple drivers, HIT# and HITM#
are activated on specific clock edges and sampled on specific clock edges.
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64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet