80546KF Datasheet, PDF (35/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Electrical Specifications
Table 2-15. AGTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit Notes
V_IL
Input Low Voltage
0.0
GTLREF - (0.10 * V_TT)
V
1,5
V_IH
Input High Voltage GTLREF + (0.10 * V_TT)
V_TT
V
2,3,5
V_OH
Output High Voltage
0.90 * V_TT
V_TT
V
3,5
I_OL
Output Low Current
V_TT /
N/A
(0.50 * Rtt_min + RON_min mA
7
|| R_L)
I_LI
Input Leakage Current
N/A
± 200
µA
6
I_LO
Output Leakage Current
N/A
± 200
µA
8
R_ON
Buffer On Resistance
8
12
W
4
NOTES:
1. V_IL is defined as the voltage level at a receiving agent that will be interpreted as a logical low value.
2. V_IH is defined as the voltage level at a receiving agent that will be interpreted as a logical high value.
3. V_IH and V_OH may experience excursions above V_CC. However, input signal drivers must comply with the signal
quality specifications in Section 3.
4. Refer to Processor Signal Integrity Models for I/V characteristics.
5. The V_TT referred to in these specifications refers to the instantaneous V_TT.
6. Leakage to V_SS with pin held at V_TT.
7. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
8. Leakage to V_TT with pin held at 300 mV.
Table 2-16. PWRGOOD and TAP Signal Group DC Specifications
Symbol
Parameter
Min
V_HYS
V_T+
V_T-
V_OH
I_OL
I_LI
I_LO
R_ON
Input Hysteresis
Input Low to High
Threshold Voltage
Input High to Low
Threshold Voltage
Output High Voltage
Output Low Current
Input Leakage Current
Output Leakage Current
Buffer On Resistance
200
0.5 * (V_TT + V_{HYS_MIN})
0.5 * (V_TT - V_{HYS_MAX})
N/A
8
Max
350
0.5 * (V_TT + V_{HYS_MAX})
0.5 * (V_TT - V_{HYS_MIN})
V_TT
45
±200
±200
12
Unit
mV
Notes¹
6
V
4
V
4
V
2,4
mA
5
µA
µA
Ω
3
NOTES:
1. All outputs are open drain.
2. TAP signal group must meet system signal quality specification in Section 3.
3. Refer to the Processor Signal Integrity Models for I/V characteristics.
4. The V_TT referred to in these specifications refers to instantaneous V_TT.
5. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
6. V_HYS represents the amount of hysteresis, nominally centered about 0.5 * V_TT for all TAP inputs.
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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