80546KF Datasheet, PDF (41/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Electrical Specifications
6. Specification for a minimum swing defined between TAP V_T- to V_T+. This assumes a minimum edge rate of
0.5 V/ns.
7. It is recommended that TMS be asserted while TRST# is being deasserted.
Table 2-26. VIDPWRGD and Other Voltage Sequence AC Specifications
T# Parameter
T70: VIDPWRGD rise time
T71: V_TT to VIDPWRGD delay time
T72: V_TT to VIDPWRGD deassertion time
T73: VIDPWRGD to V_CACHE delay time
T74: V_CACHE to V_CC delay time
Min
Max
Unit
Figure
Notes
150
ns
2-19
1
1
10
ms
2-19
1
ms
2-19
2
0
ms
2-18
1
ms
2-18
3
NOTES:
1. Rise time is measured between 10% and 90% points on the waveform.
2. Specification refers to the time between VIDPWRGD = V_TT - 20% and VIDPWRGD = V_IL.
3. V_CACHE to V_CC delay time is measured from (0.5 * CVID) to (0.5 * VID).
Table 2-27. VID Signal Group AC Timing Specifications
T# Parameter
Min
Max
Unit Figure
Notes
T80: VID Step Time
5
T81: VID Dwell Time
50
T82: VID Down Transition to Valid V_CC (min)
T82: VID Up Transition to Valid V_CC (min)
T82: VID Down Transition to Valid V_CC (max)
T82: VID Up Transition to Valid V_CC (max)
µs 2-21, 2-22
µs 2-21, 2-22
0
µs
2-21
50
µs
2-21
50
µs
2-22
0
µs
2-22
Table 2-28. SMBus Signal Group AC Specifications
T# Parameter
Min
Max
T90: SM_CLK Frequency
T91: SM_CLK Period
T92: SM_CLK High Time
T93: SM_CLK Low Time
T94: SMBus Rise Time
T95: SMBus Fall Time
T96: SMBus Output Valid Delay
T97: SMBus Input Setup Time
T98: SMBus Input Hold Time
T99: Bus Free Time
T100: Hold Time after Repeated Start
Condition
T101: Repeated Start Condition Setup
Time
T102: Stop Condition Setup Time
10
100
10
100
4.0
N/A
4.7
N/A
0.02
1.0
0.02
0.3
0.1
4.5
250
N/A
300
N/A
4.7
N/A
4.0
N/A
4.7
N/A
4.0
N/A
Unit Figure
KHz
µs
µs
2-16
µs
2-16
µs
2-16
µs
2-16
µs
2-17
ns
2-16
ns
2-16
µs
2-16
µs
2-16
µs
2-16
µs
2-16
Notes ^1,2
4
4
3,5
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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