80546KF Datasheet, PDF (107/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Features
Figure 8-1. Stop Clock State Machine
Normal State
Normal execution
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
INIT#, BINIT#, INTR, NMI, SMI#,
RESET#, FSB interrupts
Enhanced HALT or HALT State
BCLK running
Snoops and interrupts allowed
STPCLK#
Asserted
STPCLK#
De-asserted
Stop Grant State
BCLK running
Snoops and interrupts allowed
STAPsCsLeKrt#eSdTDPeC-LaKss#erted
Snoop Event Occurs
Snoop Event Serviced
Snoop Snoop
Event Event
Occurs Serviced
Enhanced HALT Snoop or HALT
Snoop State
BCLK running
Service snoops to caches
Stop Grant Snoop State
BCLK running
Service snoops to caches
8.2.3
Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks
after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Both
logical processors must be in the Stop-Grant state before the deassertion of STPCLK#.
Since the AGTL+ signal pins receive power from the front side bus, these pins should not be driven
(allowing the level to return to V_TT) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the front side bus should be driven to the inactive state.
BINIT# is not serviced while the processor is in Stop-Grant state. The event is latched and can be
serviced by software upon exit from the Stop-Grant state.
RESET# causes the processor to immediately initialize itself, but the processor will stay in Stop-
Grant state. A transition back to the Normal state occurs with the deassertion of the STPCLK#
signal.
A transition to the Grant Snoop state occurs when the processor detects a snoop on the front side
bus (see Section 8.2.4).
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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