80546KF Datasheet, PDF (54/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Front Side Bus Signal Quality Specifications
Table 3-1. Ringback Specifications for AGTL+ and GTL+ Asynchronous Signal Groups
Signal Group
Maximum Ringback
Transition (with Input Diodes Present) Unit Figure
Notes
AGTL+, Async GTL+ Low → High
AGTL+, Async GTL+ High → Low
GTLREF + (0.06 * V_TT)
GTLREF - (0.06 * V_TT)
V
3-1
1,2,3,4,5,6
V
3-2
1,2,3,4,5,6
NOTES:
1. All signal integrity specifications are measured at the processor core (pads).
2. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
3. Specifications are for the edge rate of 1.8- 2.2V/ns.
4. All values specified by design characterization.
5. Please see Section 3.1.3 for maximum allowable overshoot.
6. The total ringback tolerance is 6% of V_TT (0.06 * V_TT). This consists of 4% AC and 2% DC components.
Ringback between GTLREF + (0.06 * V_TT) and GTLREF - (0.06 * V_TT) is not supported.
Figure 3-1. Low-to-High Front Side Bus Receiver Ringback Tolerance
V_TT
+ 6% * VTT
GTLREF
– 6% * VTT
V_SS
Figure 3-2. High-to-Low Front Side Bus Receiver Ringback Tolerance
V_TT
+ 6% * VTT
GTLREF
- 6% * VTT
V_SS
Noise Margin
Noise Margin
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64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet