80546KF Datasheet, PDF (123/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Features
8.4.9.5
8.4.9.6
8.4.9.4.7 L2/L3 Cache Size
Offset 27 - 28h is the L2 cache size field. The field reflects the size of the level two cache in
kilobytes. Offset 29 - 3Ah is the L3 cache size field and also reflects size in kilobytes. Both fields
are in hex format.
Example: The 64-bit Intel^® Xeon™ processor MP with up to 8MB L3 cache has a 1 MB
(1024 KB) L2 cache and either 4 MB (4096 KB) or 8 MB (8192 KB) L3 cache. Thus, offset 27 -
28h will contain 0400h, and offset 29 - 2Ah will contain 1000h (for 4 MB) or 2000h (for 8 MB).
8.4.9.4.8 Cache Voltage
There are two areas defined in the PIROM for the L3 cache voltages associated with the processor.
Offset 2B - 2Ch is the Processor Cache VID (Cache Voltage Identification), or CVID, field and
contains the voltage requested via the CVID pins. In the case of the 64-bit Intel^® Xeon™ processor
MP with up to 8MB L3 cache, this is 1.275 V. This field is in mV and is reflected in hex. This data
is also in Table 2-9. Some systems read this offset to determine if all processors support the same
default CVID setting.
Minimum L3 cache voltage specifications are reflected in offset 2D - 2Eh. This field is in mV and
reflected in hex. This data is also in Table 2-9. For processors that follow a load line DC
specification, the minimum V_CACHE reflected in this field should reflect the minimum allowable
voltage at maximum current.
Example: The specifications for a 64-bit Intel^® Xeon™ processor MP with up to 8MB L3 cache
are 1.275 V CVID and 1.125 V minimum voltage (at maximum current). Offset 2B - 2Ch would
contain 04FBh (1275 decimal) and offset 2D - 2Eh would contain 0465h (1125 decimal).
Package Data
This section describes the package revision location at offset 32 - 35h. This field tracks the highest
level revision. It is provided in ASCII format of four characters (8 bits x 4 characters = 32 bits).
The package is documented as 1.0, 2.0, etc. Because this only consumes three ASCII characters, a
leading space is provided in the data field.
Example: The C-0 stepping of the 64-bit Intel^® Xeon™ processor MP with up to 8MB L3 cache
utilizes revision 1.0 of the FC-mPGA package. Thus, at offset 32-35h, the data is a space followed
by 1.0. In hex, this would be 20, 31, 2E, 30.
Part Number Data
This section provides traceability. There are 208 available bytes in this section for future use.
8.4.9.6.9 Processor Part Number
Offset 38 - 3Eh contains seven ASCII characters reflecting the Intel part number for the processor.
This information is typically marked on the outside of the processor. If the part number is less than
7 characters, a leading space is inserted into the value. The part number should match the
information found in the marking specification found in Section 4.
Example: A processor with a part number of 80546KF will have data found at offset 38 - 3Eh is
38, 30, 35, 34, 36, 4B, 46.
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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