 English |
|
|
|
|
|
|
|
| 80546KF Datasheet, PDF (46/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache | |||
| |||
| ◁ |
Electrical Specifications
Figure 2-12. Source Synchronous 4X (Data) Timing Waveform
T0
T1
T2
TP/4 TP/2 3TP/4
BCLK1
BCLK0
DSTBp# (@ driver)
DSTBn# (@ driver)
TH
TD
TA TB TA TB
D# (@ driver)
TJ
TC
DSTBp# (@ receiver)
DSTBn# (@
receiver)
D# (@ receiver)
TE TG TE TG
TP = T1: BCLK[1:0] Period
TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe
TB = T22: Source Sync. Data Output Valid Delay After Data Strobe
TC = T27: Source Sync. Input Setup Time to BCLK
TD = T31: Data Strobe 'n' (DSTBN#) Output Valid Delay
TE = T25: Source Sync. Input Setup Time
TG = T26: Source Sync. Input Hold Time
TH = T30: First Data Strobe to Subsequent Strobes
TJ = T20: Source Sync. Data Output Valid Delay
46
64-bit Intel® Xeon⢠Processor MP with up to 8MB L3 Cache Datasheet
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese