80546KF Datasheet, PDF (23/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Electrical Specifications
2.3
Cache Voltage Identification (CVID)
The CVID[3:0] pins supply the encodings that determine the voltage to be supplied by the V_CACHE
(the L3 cache voltage for the processor) voltage regulator. The CVID specification for the
processor is defined by the VRM 9.1 DC-DC Converter Design Guidelines, Voltage Regulator
Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.1 Design Guidelines, Voltage
Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.2 Design
Guidelines, and Voltage Regulator Module (VRM)10.2L Design Guidelines. The voltage set by the
CVID pins is the maximum V_CACHE voltage allowed by the processor. A minimum V_CACHE
voltage is provided in Table 2-9.
Processors with the same front side bus frequency, internal cache sizes, and stepping will have
consistent CVID values.
The processor uses four voltage identification pins (CVID[3:0]) to support automatic selection of
power supply voltages. Table 2-4 specifies the voltage level corresponding to the state of
CVID[3:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If
the processor socket is empty, or the voltage regulation circuit cannot supply the voltage that is
requested, the processor’s voltage regulator must disable itself.
Table 2-4. Cache Voltage Identification (CVID) Definition
CVID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
CVID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
CVID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
CVID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
CVID (V)
Off
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
NOTE: The voltage regulator will have a fifth VID input and, for VRM 10.2-compliant regulators, a sixth VID
input as well. The extra input(s) should be tied to a high voltage on the motherboard for correct
operation.
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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