80546KF Datasheet, PDF (109/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Features
Note: Not all processors are capable of supporting Enhanced Intel SpeedStep technology. More details on
which processor frequencies will support this feature will be provided in future releases of the
Specification Update.
Enhanced Intel SpeedStep technology is a technology that creates processor performance states
(P-states). P-states are power consumption and capability states within the Normal state. Enhanced
Intel SpeedStep technology enables real-time dynamic switching between frequency and voltage
points. It alters the performance of the processor by changing the bus to core frequency ratio and
voltage. This allows the processor to run at different core frequencies and voltages to best serve the
performance and power requirements of the processor and system. Note that the front side bus is
not altered; only the internal core frequency is changed. In order to run at reduced power
consumption, the voltage is altered in step with the bus ratio.
The following are key features of Enhanced Intel SpeedStep technology:
• Multiple voltage/frequency operating points provide optimal performance at reduced power
consumption.
• Voltage/frequency selection is software controlled by writing to processor MSR’s (Model
Specific Registers), thus eliminating chipset dependency.
— If the target frequency is higher than the current frequency, V_CC is incremented in steps
(+12.5 mV) by placing a new value on the VID signals and the processor shifts to the new
frequency. Note that the top frequency for the processor can not be exceeded.
— If the target frequency is lower than the current frequency, the processor shifts to the new
frequency and V_CC is then decremented in steps (-12.5 mV) by changing the target VID
through the VID signals.
8.4
System Management Bus (SMBus) Interface
The processor package includes an SMBus interface which allows access to a memory component
with two sections (referred to as the Processor Information ROM and the Scratch EEPROM) and a
thermal sensor on the substrate. The SMBus thermal sensor may be used to read the thermal diode
mentioned in Section 7.2.8. These devices and their features are described below.
The SMBus thermal sensor and its associated thermal diode are not related to and are completely
independent of the precision, on-die temperature sensor and thermal control circuit (TCC) of the
Thermal Monitor or Thermal Monitor 2 features discussed in Section 7.2.1.
The processor SMBus implementation uses the clock and data signals of the System Management
Bus (SMBus) Specification. It does not implement the SMBSUS# signal.
For platforms which do not implement any of the SMBus features found on the processor, all of the
SMBus connections, except SM_VCC, to the socket pins may be left unconnected (SM_ALERT#,
SM_CLK, SM_DAT, SM_EP_A[2:0], SM_TS_A[1:0], SM_WP).
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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