80546KF Datasheet, PDF (12/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Introduction
ECC protection (single-bit error correction with double-bit error detection), and the bus protocol
addition of the Deferred Phase. Further details can be found in the 64-bit Extension Technology
Software Developer’s Guide at http://developer.intel.com/technology/64bitextensions/.
The 64-bit Intel^® Xeon™ processor MP with up to 8MB L3 cache is intended for high performance
multi-processor server systems with support for up to two processors on a 667 MHz front side bus.
The 64-bit Intel^® Xeon™ processor MP with up to 8MB L3 cache will be available with 4 MB or
8 MB of on-die level 3 (L3) cache. All versions of the processor will include manageability
features. Components of the manageability features include an OEM EEPROM and Processor
Information ROM which are accessed through an SMBus interface and contain information
relevant to the particular processor and system in which it is installed.
Table 1-1. Features of the 64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache
Processor
# of
Symmetric
Agents
1-255
# of Supported
Symmetric Agents
Per FSB
L2 Advanced
Transfer Cache
1-2
1 MB
Integrated L3
Cache
4 MB or 8 MB
FSB
Frequency
667 MHz
The processor is packaged in a 604-pin Flip-Chip Micro Pin Grid Array (FC-mPGA4) package and
utilizes a surface-mount Zero Insertion Force (ZIF) mPGA604 socket.
The processor uses a scalable system bus referred to as the “Front Side Bus” (FSB) in this
document. The FSB utilizes a split-transaction, deferred reply and modified enhanced deferred
phase protocol that improves bandwidth and throughput by reducing the number of cycles needed
to return data from a deferred response. The front side bus uses Source-Synchronous Transfer
(SST) of address and data to improve performance. The processor transfers data four times per bus
clock (4X data transfer rate). Along with the 4X data bus, the address bus can deliver addresses two
times per bus clock and is referred to as a ‘double-clocked’, ‘double-pumped’, or the 2X address
bus. In addition, the Request Phase completes in one clock cycle. Working together, the 4X data
bus and 2X address bus provide a data bus bandwidth of up to 5.3 GB per second. Finally, the front
side bus is also used to deliver interrupts.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating that a signal is in the
asserted state when driven to a low level. For example, when RESET# is low (i.e. when RESET# is
asserted), a reset has been requested. Conversely, when NMI is high (i.e. when NMI is asserted), a
nonmaskable interrupt request has occurred. In the case of signals where the name does not imply
an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol
implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# =
‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“Front side bus” refers to the interface between the processor, system core logic (i.e. the chipset
components), and other bus agents. The front side bus supports multiprocessing and cache
coherency. For this document, “front side bus” is used as the generic term for the processor system
bus.
Commonly used terms are explained here for clarification:
• 64-bit Intel^® Xeon™ processor MP with up to 8MB L3 cache — The entire product,
including processor core substrate and integrated heat spreader (IHS).
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64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet