80546KF Datasheet, PDF (93/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Signal Definitions
Table 6-1. Signal Definitions (Sheet 7 of 9)
Name
RS[2:0]#
RSP#
SKTOCC#
SLEW_CTRL
SM_ALERT#
SM_CLK
SM_DAT
SM_EP_A[2:0]
SM_TS_A[1:0]
SM_VCC
SM_WP
Type
Description
RS[2:0]# (Response Status) are driven by the response agent (the agent
I responsible for completion of the current transaction), and must connect to the
appropriate pins of all processor front side bus agents.
RSP# (Response Parity) is driven by the response agent (the agent
responsible for completion of the current transaction) during assertion of
RS[2:0]#, the signals for which RSP# provides parity protection. It must
connect to the appropriate pins of all processor front side bus agents.
I
A correct parity signal is electrically high if an even number of covered signals
are electrically low and electrically low if an odd number of covered signals are
electrically low. If RS[2:0]# are all electrically high, RSP# is also electrically
high, since this indicates it is not being driven by any agent guaranteeing
correct parity.
SKTOCC# (Socket occupied) will be pulled to ground by the processor to
O indicate that the processor is present. There is no connection to the processor
silicon for this signal.
SLEW_CTRL must be terminated to V_SS on the baseboard using precision
I resistors. This input configures the slew rate of the AGTL+ drivers. Refer to
Table 2-19 for implementation details.
SM_ALERT# (SMBus Alert) is an asynchronous interrupt line associated with
O
the SMBus Thermal Sensor device. It is an open-drain output and the
processor includes a 10kΩ pull-up resistor to SM_VCC for this signal. For more
information on the usage of the SM_ALERT# pin, see Section 8.4.7.
The SM_CLK (SMBus Clock) signal is an input clock to the system
management logic which is required for operation of the system management
I/O features of the processor. This clock is driven by the SMBus controller and is
asynchronous to other clocks in the processor.The processor includes a 10 kΩ
pull-up resistor to SM_VCC for this signal.
The SM_DAT (SMBus Data) signal is the data signal for the SMBus. This signal
I/O
provides the single-bit mechanism for transferring data between SMBus
devices. The processor includes a 10k Ω pull-up resistor to SM_VCC for this
signal.
The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in
conjunction with the upper address bits in order to maintain unique addresses
on the SMBus in a system with multiple processors. To set an SM_EP_A line
I
high, a pull-up resistor should be used that is no larger than 1 kΩ. The
processor includes a 10 kΩ pull-down resistor to V_SS for each of these signals.
For more information on the usage of these pins, see Section 8.4.8.
The SM_TS_A (Thermal Sensor Select Address) pins are decoded on the
SMBus in conjunction with the upper address bits in order to maintain unique
addresses on the SMBus in a system with multiple processors.
I The device’s addressing, as implemented, includes a Hi-Z state for both
address pins. The use of the Hi-Z state is achieved by leaving the input floating
(unconnected).
For more information on the usage of these pins, see Section 8.4.8.
I
SM_VCC provides power to the SMBus components on the processor
package.
WP (Write Protect) can be used to write protect the Scratch EEPROM. The
I Scratch EEPROM is write-protected when this input is pulled high to SM_VCC.
The processor includes a 10 kΩ pull-down resistor to V_SS for this signal.
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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