80546KF Datasheet, PDF (40/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Electrical Specifications
Table 2-23. Miscellaneous Signals AC Specifications (Sheet 2 of 2)
T# Parameter
Min
Max
Unit
Figure
Notes
1,2,5
T38: PROCHOT#, FORCEPR# pulse width
T39: THERMTRIP# assertion until V_CC and
V_CACHE removal
T40: FERR# valid delay from STPCLK#
deassertion
T41: V_CC to PWRGOOD assertion time
500
µs
2-14
4
500
ms
2-15
6
0
5
BCLKs 2-20
1
500
ms
2-18
NOTES:
1. All AC timings for the GTL+ asynchronous signals are referenced to the BCLK0 rising edge at Crossing
Voltage (V_CROSS). All GTL+ asynchronous signal timings are referenced at GTLREF. PWRGOOD is
referenced to the BCLK0 rising edge at 0.5 * V_TT.
2. These signals may be driven asynchronously.
3. Refer to the PWRGOOD definition for more details regarding the behavior of the signal.
4. Length of assertion for PROCHOT# does not equal TCC activation time. Time is required after the assertion
or deassertion of PROCHOT# for the processor to enable or disable the TCC. Additionally, time is allocated
after the assertion or deassertion of PROCHOT# for the processor to complete current instruction execution.
This specification applies to the PROCHOT# signal when asserted by the processor and the FORCEPR#
signal when asserted by the system.
5. Refer to Section 8.2 for additional timing requirements for entering and leaving low power states.
6. Intel recommends the V_TT power supply also be removed upon assertion of THERMTRIP#.
7. A minimum pulse width of 500us is recommended when FORCEPR# is asserted by the system.
Table 2-24. Front Side Bus AC Specifications (Reset Conditions)
T# Parameter
Min
T47: Reset Configuration Signals (A[21:16]#)
Setup Time
1
T45: Reset Configuration Signals (A[39:22]#,
A[15:3]#, BR[3:0]#, INIT#, SMI#) Setup Time
4
T46: Reset Configuration Signals (A[39:3]#,
BR[3:0]#, INIT#, SMI#) Hold Time
2
Max
Unit Figure Notes
ms
1
BCLKs 2-18
1
28
BCLKs 2-18
2
NOTES:
1. Before the clock that de-asserts RESET#
2. After the clock that de-asserts RESET#.
Table 2-25. TAP Signal Group AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1,7
T55: TCK Period
T61: TDI, TMS Setup Time
T62: TDI, TMS Hold Time
T63: TDO Clock to Output Delay
T64: TRST# Assert Time
13.3
ns
2-7
2
1.5
ns
2-13
3,6
3.0
ns
2-13
3,6
0.5
10.0
ns
2-13
4
2
TCK
2-14
5
NOTES:
1. Not 100% tested. These parameters are based on design characterization.
2. This specification is based on the capabilities of the ITP-XDP debug port tool, not on processor silicon.
3. Referenced to the rising edge of TCK.
4. Referenced to the falling edge of TCK.
5. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.
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64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet