80546KF Datasheet, PDF (17/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

2 Electrical Specifications
2.1
Front Side Bus and GTLREF
Most processor front side bus (FSB) signals use Assisted Gunning Transceiver Logic (AGTL+)
signaling technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. AGTL+ buffers are open-drain and require
pull-up resistors to provide the high logic level and termination. AGTL+ output buffers differ from
GTL+ buffers with the addition of an active pMOS pull-up transistor to “assist” the pull-up
resistors during the first clock of a low-to-high voltage transition. Platforms implement a
termination voltage level for AGTL+ signals defined as V_TT. Because platforms implement
separate power planes for each processor, separate V_CC and V_TT supplies are necessary. This
configuration allows for improved noise tolerance as processor frequency increases. Speed
enhancements to data and address busses have caused signal integrity considerations and platform
design methods to become even more critical than with previous processor families.
The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard
(see Table 2-19 for GTLREF specifications). The on-die termination resistors are a selectable
feature and can be enabled or disabled via the ODTEN signal. For end bus agents, on-die
termination resistors are enabled to control reflections on the transmission line. For the middle bus
agent, on-die termination R_TT resistors must be disabled. Intel chipsets will also provide on-
termination, thus eliminating the need to terminate the bus on the motherboard for most AGTL+
signals. Processor wired-OR signals may also include additional on-die resistors (R_L) to further
ensure proper noise margin and signal integrity. R_L is not configurable and is always enabled for
these signals. See Table 2-6 for a list of these signals.
Figure 2-1 illustrates the active on-die termination.
Figure 2-1. On-Die Front Side Bus Termination
End Agent
Middle Agent
V_TT
R_TT
Signal
R_L
Signal
R_TT - On-die termination resistors for AGTL+ signals
R_L - Additional on-die resistance implemented for proper noise margin and
signal integrity (wired-OR signals only)
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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