80546KF Datasheet, PDF (122/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Features
Example: The processor supports a 667 MHz front side bus. Therefore, offset 1A - 1Bh has a value
of 029Bh.
8.4.9.3.3 Multi-Processor Support
Offset 1Ch has 2 bits defined for representing the supported number of physical processors on the
bus. These two bits are MSB aligned where 00b equates to single-processor operation, 01b is a
dual-processor operation, and 11b represents multi-processor operation. Normally, only values of
01 and 11b are used. The remaining six bits in this field are reserved for the future use.
8.4.9.3.4 Maximum Core Frequency
Offset 1D - 1Eh provides the maximum core frequency for the processor. The frequency should
equate to the markings on the processor and/or the QDF/S-spec speed even if the parts are not
limited or locked to the intended speed. Format of this field is in MHz, rounded to a whole number,
and encoded in hex format.
Example: A 3.00 GHz processor will have a value of 0BB8h, which equates to 3000 decimal.
8.4.9.3.5 Core Voltage
There are two areas defined in the PIROM for the core voltages associated with the processor.
Offset 1F - 20h is the Processor Core VID (Voltage Identification) field and contains the voltage
requested via the VID pins. In the case of the 64-bit Intel^® Xeon™ processor MP with up to 8MB
L3 cache, this is 1.3875 V. This field, rounded to the next thousandth, is in mV and is reflected in
hex. This data is also in Table 2-9. Some systems read this offset to determine if all processors
support the same default VID setting.
Minimum core voltage is reflected in offset 21 - 22h. This field is in mV and reflected in hex. The
minimum V_CC reflected in this field is the minimum allowable voltage assuming the FMB
maximum current draw.
Note: The minimum core voltage value in offset 21 - 22h is a single value that assumes the FMB
maximum current draw. Refer to Table 2-10 for the minimum core voltage specifications based on
actual real-time current draw.
Example: The specifications for a 64-bit Intel^® Xeon™ processor MP with up to 8MB L3 cache at
FMB are 1.3875 V VID and 1.229 V minimum voltage. Offset 1F - 20h would contain 056Ch
(1388 decimal) and offset 21 - 22h would contain 04D2h (1234 decimal).
8.4.9.3.6 T_CASE Maximum
The last field within Processor Core Data is the T_CASE Maximum field. The field reflects
temperature in degrees Celsius in hex format. This data can be found in the Table 7-1. The thermal
specifications are specified at the case (IHS).
8.4.9.4
Cache Data
This section contains cache-related data.
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64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet