80546KF Datasheet, PDF (50/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Electrical Specifications
Figure 2-19. VIDPWRGD Timing Requirements
90%
80%
10%
V
TT
Ta
V_IH
VIDPWRGD
V_IL
Tb
Ta
=
T71
V
TT
to
VIDPWRGD
delay
time
Tb = T70 VIDPWRGD rise time
Tc = T72 V to VIDPWRGD deassertion time
TT
Figure 2-20. FERR#/PBE# Valid Delay Timing
V_IL
Tc
BCLK
system bus
SG
Ack
STPCLK#
FERR#/
FERR# undefined
PBE#
PBE#
Ta
undefined FERR#
Ta = T40: FERR# valid delay from STPCLK# de-assertion
Note: FERR#/PBE# is also undefined from STPCLK# assertion until the stop grant acknowledge is driven on
the processor system bus. FERR#/PBE# is also undefined for a period of Ta from STPCLK# de-assertion.
Inside these undefined regions the PBE# signal is driven. FERR# is driven at all other times.
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64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet