80546KF Datasheet, PDF (89/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Signal Definitions
Table 6-1. Signal Definitions (Sheet 3 of 9)
Name
Type
Description
BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The
BREQ[3:0]# signals are interconnected in a rotating manner to individual
processor pins. The tables below give the rotating interconnect between the
processor and bus signals for 3-load configurations.
BR0#
BR[3:1]#
BR[1:0]# Signals Rotating Interconnect, 3-Load Configuration
Bus Signal Agent 0 Pins Agent 1 Pins
I/O
BREQ0#
BR0#
I
BREQ1#
BR1#
BR1#
BR0#
BSEL[1:0]
COMP0
CVID[3:0]
D[63:0]#
DBI[3:0]#
BR2# and BR3# must not be utilized in 3-load configurations. However, they
must still be terminated.
During power-on configuration, the central agent must assert the BR0# bus
signal. All symmetric agents sample their BR[3:0]# pins on the active-to-
inactive transition of RESET#. The pin which the agent samples asserted
determines its agent ID.
These output signals are used to select the front side bus frequency. The
frequency is determined by the processor(s), chipset, and frequency
synthesizer capabilities. All front side bus agents must operate at the same
O _{frequency. Individual processors will only operate at their specified front side}
bus frequency.
See Table 2-2 for output values.
I
COMP0 must be terminated to V_SS on the baseboard using precision resistors.
This input configures the AGTL+ drivers of the processor. Refer to Table 2-19.
CVID[3:0] (Cache Voltage ID) pins are used to support automatic selection of
V_CACHE. These are open drain signals that are driven by the processor and
must be pulled to no more than 3.3 V (+5% tolerance) with a resistor.
O
Conversely, the V_CACHE VR output must be disabled prior to the voltage supply
for these pins becoming invalid. The CVID pins are needed to support
processor voltage specification variations. See Table 2-4 for definitions of these
pins. The V_CACHE VR must supply the voltage that is requested by these pins,
or disable itself.
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path
between the processor front side bus agents, and must connect the appropriate
pins on all such agents. The data driver asserts DRDY# to indicate a valid data
transfer.
D[63:0]# are quad-pumped signals, and will thus be driven four times in a
common clock period. D[63:0]# are latched off the falling edge of both
I/O DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a
pair of one DSTBP# and one DSTBN#. The following table shows the grouping
of data signals to strobes and DBI#.
Furthermore, the DBI# pins determine the polarity of the data signals. Each
group of 16 data signals corresponds to one DBI# signal. When the DBI# signal
is active, the corresponding data group is inverted and therefore sampled
active high.
DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# and
DEP[7:0]# signals. The DBI[3:0]# signals are activated when the data on the
I/O
data bus is inverted. If more than half the data bits, within an 18-bit group
(including ECC bits), would have been asserted electrically low, the bus agent
may invert the data bus and corresponding ECC signals for that particular sub-
phase for that 18-bit group.
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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