80546KF Datasheet, PDF (45/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Electrical Specifications
Figure 2-11. Source Synchronous 2X (Address) Timing Waveform
T1
T2
T_P/4 T_P/2 3T_P/4
BCLK1
BCLK0
T_Q
ADSTB# (@ driver)
T_R
T_H
T_J
T_H
T_J
A# (@ driver)
valid
valid
T_K
T_S
ADSTB# (@ receiver)
A# (@ receiver)
valid
valid
T_M
T_N
T_P = T1: BCLK[1:0] Period
T_H = T23: Source Sync. Address Output Valid Before Address Strobe
T_J = T24: Source Sync. Address Output Valid After Address Strobe
T_K = T27: Source Sync. Input Setup Time to BCLK
T_M = T25: Source Sync. Input Setup Time
T_N = T26: Source Sync. Input Hold Time
T_Q = T29: First Address Strobe to Second Address Strobe
T_S = T20: Source Sync. Output Valid Delay
T_R = T32: Address Strobe Output Valid Delay
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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