80546KF Datasheet, PDF (25/138 Pages) Intel Corporation – 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache

Electrical Specifications
2.6
Front Side Bus Signal Groups
The front side bus signals are grouped by buffer type as listed in Table 2-5. The buffer type
indicates which AC and DC specifications apply to the signals. AGTL+ input signals have
differential input buffers that use GTLREF as a reference level. In this document, the term “AGTL+
Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly,
“AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
AGTL+ asynchronous outputs can become active anytime and include an active pMOS pull-up
transistor to assist during the first clock of a low-to-high voltage transition.
Implementing a source synchronous data bus requires specifying two sets of timing parameters.
One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#,
HIT#, HITM#, etc.). The second set is for the source synchronous signals that are relative to their
respective strobe lines (data and address) as well as the rising edge of BCLK0. Asynchronous
signals are present (A20M#, IGNNE#, etc.) and can become active at any time during the clock
cycle. Table 2-5 identifies signals as common clock, source synchronous, and asynchronous.
Table 2-5. Front Side Bus Pin Groups (Sheet 1 of 2)
Signal Group
Type
Signals¹
AGTL+ Common Clock Input
AGTL+ Common Clock I/O
Synchronous to BCLK[1:0]
Synchronous to BCLK[1:0]
BPRI#, BR[3:1]#, DEFER#, ID[7:0]#, IDS#,
OOD#, RESET#, RS[2:0]#, RSP#, TRDY#
ADS#, AP[1:0]#, BINIT#, BNR#, BPM[5:0]#,
BR0#, DBSY#, DP[3:0]#, DRDY#, HIT#,
HITM#, LOCK#, MCERR#
AGTL+ Source Synchronous
I/O
Synchronous to associated
strobe
Signals
Associated Strobe
REQ[4:0]#,
A[37:36,16:3]#
A[39:38,35:17]#
D[15:0]#, DEP[1:0]#,
DBI0#
D[31:16]#, DEP[3:2]#,
DBI1#
D[47:32]#, DEP[5:4]#,
DBI2#
D[63:48]#, DEP[7:6]#,
DBI3#
ADSTB0#
ADSTB1#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
AGTL+ Strobe Input/Output Synchronous to BCLK[1:0]
AGTL+ Asynchronous Output Asynchronous
GTL+ Asynchronous Input
Asynchronous
GTL+ Asynchronous Output
TAP Input
TAP Input
TAP Output
Asynchronous
Synchronous to TCK
Asynchronous
Synchronous to TCK
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
FERR#/PBE#, IERR#, PROCHOT#
A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/
INTR, LINT1/NMI, SMI#, STPCLK#
THERMTRIP#
TCK, TDI, TMS
TRST#
TDO
64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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