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Signal Definitions
Table 6-1. Signal Definitions (Sheet 6 of 9)
Name
MCERR#
ODTEN
OOD#
PROCHOT#
PWRGOOD
REQ[4:0]#
RESET#
Type
Description
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error
or a bus protocol violation. It may be driven by all processor front side bus
agents.
MCERR# assertion conditions are configurable at a system level. Assertion
options are defined as follows:
• Enabled or disabled.
• Asserted, if configured, for internal errors along with IERR#.
• Asserted, if configured, by the request initiator of a bus transaction after it
I/O
observes an error.
• Asserted by any bus agent when it observes an error in a bus transaction.
For more details regarding machine check architecture, refer to the IA-32 Intel®
Software Developer’s Manual, Volume 3: System Programming Guide.
Since multiple agents may drive this signal at the same time, MCERR# is a
wired-OR signal which must connect the appropriate pins of all processor front
side bus agents. In order to avoid wire-OR glitches associated with
simultaneous edge transitions driven by multiple drivers, MCERR# is activated
on specific clock edges and sampled on specific clock edges.
ODTEN (On-die termination enable) should be connected to V_TT through a
resistor to enable on-die termination for end bus agents. For middle bus
I agents, pull this signal down via a resistor to ground to disable on-die
termination. Whenever ODTEN is high, on-die termination will be active,
regardless of other states of the bus.
I
OOD# allows data delivery to occur subsequent to IDS# assertion during the
Deferred Phase.
O
The assertion of PROCHOT# (processor hot) indicates that the processor die
temperature has reached its thermal limit. See Section 7.2.4 for more details.
PWRGOOD (Power Good) is an input. The processor requires this signal to be
a clean indication that all processor clocks and power supplies are stable and
within their specifications. “Clean” implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time that the
power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high state. Figure 2-18 illustrates the
relationship of PWRGOOD to the RESET# signal. PWRGOOD can be driven
I
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD. It must also meet the minimum pulse
width specification in Table 2-21, and be followed by a 1 ms active RESET#
pulse.
The PWRGOOD signal must be supplied to the processor. This signal is used
to protect internal circuits against voltage sequencing issues. It should be
driven high throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate pins of all
processor front side bus agents. They are asserted by the current bus owner to
I/O define the currently active transaction type. These signals are source
synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal description for
details on parity checking of these signals.
Asserting the RESET# signal resets all processors to known states and
invalidates their internal caches without writing back any of their contents. For a
power-on Reset, RESET# must stay active for at least 1 ms after VCC and
BCLK have reached their specified levels. On observing active RESET#, all
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front side bus agents will deassert their outputs within two clocks. RESET#
must not be kept asserted for more than 10 ms.
A number of bus signals are sampled at the active-to-inactive transition of
RESET# for power-on configuration. These configuration options are described
in Section 8.1.
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64-bit Intel^® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet