MC68HC908GP20 Datasheet, PDF (89/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

INTERNAL
DATA BUS
READ DDRB/DDRB
WRITE DDRB/DDRD
RESET
WRITE PTB
READ PTB
DDRBx
PTBx
DISABLE
PTB/Dx
ADC CHANNEL x
ADC DATA REGISTER
DISABLE
ADC
CONVERSION
VOLTAGE IN
INTERRUPT ^COMPLETE
ADC
LOGIC
(ADV_IN) _CHANNEL ^{ADCH4–ADCH0}
SELECT
AIEN COCO
CGMXCLK
BUS CLOCK
ADC CLOCK
CLOCK
GENERATOR
ADIV2–ADIV0 ADICLK
Figure 5-1. ADC Block Diagram
5.4.1 ADC Port I/O Pins
PTB7/AD7–PTB0/AD0 are general-purpose I/O (input/output) pins
that share with the ADC channels. The channel select bits define which
ADC channel/port pin will be used as the input signal. The ADC
overrides the port I/O logic by forcing that pin as input to the ADC. The
remaining ADC channels/port pins are controlled by the port I/O logic
and can be used as general-purpose I/O. Writes to the port register or
DDR will not have any affect on the port pin that is selected by the ADC.
Read of a port pin in use by the ADC will return a logic 0.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
89