MC68HC908GP20 Datasheet, PDF (340/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

SPTIE— SPI Transmit Interrupt Enable
This read/write bit enables CPU interrupt requests generated by the
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
20.14.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these
conditions:
• Receive data register full
• Failure to clear SPRF bit before next byte is received (overflow
error)
• Inconsistent logic level on SS pin (mode fault error)
• Transmit data register empty
The SPI status and control register also contains bits that perform these
functions:
• Enable error interrupts
• Enable mode fault error detection
• Select master SPI baud rate
Address: $0011
Read:
Write:
Bit 7
SPRF
6
ERRIE
5
OVRF
4
MODF
3
SPTE
2
MODFEN
1
SPR1
Bit 0
SPR0
Reset: 0
0
0
0
1
0
0
0
= Unimplemented
Figure 20-14. SPI Status and Control Register (SPSCR)
Advance Information
340
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor