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| MC68HC908GP20 Datasheet, PDF (383/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers | |||
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Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Low-voltage inhibit, trip falling voltage â target
VTRIPF
2.5
2.6
2.63
V
Low-voltage inhibit, trip rising voltage â target
VTRIPR
2.6
2.66
2.73
V
Low-voltage inhibit reset/recover hysteresis â target
(VTRIPF + VHYS = VTRIPR)
VHYS
â
60
POR rearm voltage(8)
VPOR
0
â
POR reset voltage(9)
VPORRST
0
700
POR rise time ramp rate(10)
RPOR
0.02
â
â
mV
100
mV
800
mV
â
V/ms
Notes:
1. VDD = 3.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fosc = 16.4 MHz). All inputs 0.2 V from rail. No
dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fosc = 16.4 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait
IDD. Measured with PLL and LVI enabled.
5. Stop IDD is measured with OSC1 = VSS.
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2 V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Pullups and pulldowns are disabled.
8. Maximum is highest voltage that POR is guaranteed.
9. Maximum is highest voltage that POR is possible.
10. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
MC68HC908GP20 â Rev 2.1
Freescale Semiconductor
Advance Information
383
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