MC68HC908GP20 Datasheet, PDF (372/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE:DMAxS = 1:0),
clear CHxF by reading TIM channel x status and control register with
CHxF set and then writing a logic 0 to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic 0 to CHxF has no effect. Therefore, an interrupt request cannot
be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupts and TIM DMA service
requests on channel x. The DMAxS bit in the TIM DMA select register
selects channel x TIM DMA service requests or TIM CPU interrupt
requests.
NOTE:
TIM DMA service requests cannot be used in buffered PWM mode. In
buffered PWM mode, disable TIM DMA service requests by clearing the
DMAxS bit in the TIM DMA select register.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests and DMA service requests
enabled
0 = Channel x CPU interrupt requests and DMA service requests
disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status and
control registers.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Advance Information
372
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor