MC68HC908GP20 Datasheet, PDF (174/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

11.6 FLASH Erase Operation
Use this step-by-step procedure to erase a block of FLASH memory to
read as logic 0:
NOTE:
1. If operating voltage is below 3.6 V, set the PMPSGVLVEN bit in
the CONFIG2 register. (See 8.3 Functional Description.)
2. Set the ERASE bit, the BLK0, BLK1, FDIV0, and FDIV1 bits in the
FLASH control register. See Table 11-1 for FDIV settings. See
Table 11-2 for block sizes.
3. To ensure target portion of array is unprotected, read the FLASH
block protect register. (See 11.8 FLASH Block Protection.)
4. Write to any FLASH address with any data within the block
address range desired.
5. Set the HVEN bit.
6. Wait for a time, t_Erase.
7. Clear the HVEN bit.
8. Wait for a time, t_Kill, for the high voltages to dissipate.
9. Clear the ERASE bit.
10. After a time, t_HVD, the memory can be accessed again in read
mode.
While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Do not exceed t_Erase
maximum.
Table 11-2 shows the various block sizes which can be erased in one
erase operation. A write to a particular address will erase varying block
sizes. The first column of the table shows a particular address bit and
the second column shows the address value of that bit which will select
a particular desired erase address array (fifth column) when selected
with the appropriate BLK1 (third column) and BLK0 (fourth column) bits.
The corresponding array size that will be erased is shown in the last
column of the table as well as the critical address bits which are affected.
Advance Information
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MC68HC908GP20 — Rev 2.1
Freescale Semiconductor