MC68HC908GP20 Datasheet, PDF (347/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

21.5 Timebase Register Description
The timebase has one register, the TBCR, which is used to enable the
timebase interrupts and set the rate.
Address: $001C
Bit 7
Read: TBIF
Write:
Reset: 0
6
5
TBR2 TBR1
0
0
= Unimplemented
4
TBR0
0
3
2
0
TBIE
TACK
0
0
* PTM test mode
1
TBON
0
Figure 21-2. Timebase Control Register (TBCR)
Bit 0
TBTST*
0
TBIF — Timebase Interrupt Flag
This read-only flag bit is set when the timebase counter has rolled
over.
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
TBR2:TBR0 — Timebase Rate Selection
These read/write bits are used to select the rate of timebase interrupts
as shown in Table 21-1.
Table 21-1. Timebase Rate Selection for OSC1 = 32.768 kHz
TBR2
0
0
0
0
1
1
1
1
TBR1
0
0
1
1
0
0
1
1
TBR0
0
1
0
1
0
1
0
1
Divider
32,768
8192
2048
128
64
32
16
8
Timebase Interrupt Rate
Hz
ms
1
1000
4
250
16
62.5
256
~ 3.9
512
~2
1024
~1
2048
~0.5
4096
~0.24
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
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