MC68HC908GP20 Datasheet, PDF (140/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

NOTE:
On a FLASH device, the options except LVI5OR3 are one-time writeable
by the user after each reset. The LVI5OR3 bit is one-time writeable by
the user only after each POR (power-on reset). The CONFIG registers
are not in the FLASH memory but are special registers containing one-
time writeable latches after each reset. Upon a reset, the CONFIG
registers default to predetermined settings as shown in Figure 8-1 and
Figure 8-2.
Address: $001E
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0 _{PMPSGV- OSC- SCIBD-}
Write:
LVEN STOPENB SRC
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-1. Configuration Register 2 (CONFIG2)
Address: $001F
Bit 7
6
5
4
3
2
1
Read:
COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC
Write:
STOP
Reset: 0
0
0
0 See Note 0
0
Note: LVI5OR3 bit is only reset via POR (power-on reset)
Figure 8-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
PMPSGVLVEN — FLASH Charge Pump Select Gate Voltage
Low-Voltage Enable Bit
PMPSGVLVEN enables low-voltage mode in the charge pump voltage
regulator circuit. Setting this bit turns the voltage regulator off to
conserve power (Recommended for voltage operation below 3.6 V
where voltage regulation is not needed). Clearing this bit turns the
regulator on (default setting) for operation above 3.6 V.
1 = Voltage regulator turned off (V_DD < 3.6 V)
0 = Voltage regulator turned on (V_DD > 3.6 V) (default)
Advance Information
140
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor