MC68HC908GP20 Datasheet, PDF (365/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
22.9 I/O Signals
Port D shares four of its pins with the TIM. (There is an optional TCLK
which can be used as an external clock input to the TIM prescaler, but is
not available on this MCU.) The four TIM channel I/O pins are T1CH0,
T1CH1, T2CH0, and T2CH1 as described in 22.4 Pin Name
Conventions.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. T1CH0 and T2CH0 can be
configured as buffered output compare or buffered PWM pins.
22.10 I/O Registers
NOTE:
References to either timer 1 or timer 2 may be made in the following text
by omitting the timer number. For example, TSC may generically refer
to both T1SC AND T2SC.
These I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM control registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0, TSC1)
• TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
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