MC68HC908GP20 Datasheet, PDF (299/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

processing can resume. Figure 19-8 shows interrupt entry timing.
Figure 19-9 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared). (See Figure
19-10.)
MODULE
INTERRUPT
I BIT
IAB
IDB
R/W
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4 VECT H VECT L START ADDR
DUMMY PC–1[7:0] PC–1[15:8]
X
A
CCR V DATA H V DATA L OPCODE
Figure 19-8. Interrupt Entry Timing
MODULE
INTERRUPT
I BIT
IAB
IDB
R/W
SP – 4 SP – 3 SP – 2 SP – 1
SP
PC
PC + 1
CCR
A
X
PC – 1 [7:0] PC–1[15:8] OPCODE OPERAND
Figure 19-9. Interrupt Recovery Timing
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
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