MC68HC908GP20 Datasheet, PDF (238/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

16.6.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is
an input or an output. Writing a logic 1 to a DDRD bit enables the output
buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
Address: $0007
Bit 7
6
5
4
3
2
1
Read:
DDRD7
Write:
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
Reset: 0
0
0
0
0
0
0
Figure 16-14. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
DDRD7–DDRD0 — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD7–DDRD0, configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 16-15 shows the port D I/O logic.
NOTE: For those devices packaged in a 40-pin dual in-line package, set DDRC7
and DDRC6 to a 1 to configure PTD6 and PTD7 as outputs.
Advance Information
238
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor